1. Field of the Invention
The present invention relates to data processing systems having cache memories. More particularly, the invention relates to improving the efficiency of cache memory operations.
2. Description of the Prior Art
Data processing systems, such as microprocessors, are typically provided with an external memory for storing data or instructions, and a cache memory for caching copies of some of the data or instructions stored in memory (hereafter “data” stored in the memory or the cache can refer to either or both of data and instructions). The cache memory improves processor performance by storing data locally, so it is quicker and more efficient for the processor to access data in the cache than data in external memory. The cache stores less data than the external memory, and so, if the processor requires data that is not held in the cache, then the required data is loaded from memory into the cache before being used by the processor (these occurrences are known as a cache miss and a cache fill). It may take several cycles for the data to be fetched from memory. Also, if all the cache lines within the cache already contain data, then a cache line will need to be selected for eviction and the data within that cache line written back to memory. Thus, the efficiency of the cache memory can be dependent upon the state of the external memory when data is fetched or written back.
One system which takes the state of the external memory into account when replacing cache lines is described in U.S. Pat. No. 6,523,092 B1. This system avoids memory thrashing by comparing a memory request address with cache tags to determine if any cache entries in the cache match the address. If a cache tag of an entry does match, then allocation to that cache entry is discouraged and an alternative victim is selected. Similarly, U.S. Pat. No. 7,020,751 B2 describes a system in which one of the criteria used by a cache victim select circuit to select a victim cache line is whether or not a bank of DRAM is busy. Cache storage lines requiring a write back to a non-busy DRAM bank are selected in preference to cached storage lines requiring a write back to a busy DRAM bank. Both of these prior art systems discourage performing cache operations which involve active areas in memory.
“Memory Access Scheduling” by Scott Rixner, William J. Dally, Ujval J. Kapasi, Peter Mattson and John D. Owens recognises that the bandwidth and latency of a memory system are dependent upon the manner in which memory accesses interact with the “3-D” structure of banks, rows, and columns characteristic of contemporary DRAM chips. Sequential accesses within the same row of DRAM have low latency compared to accesses to different rows, and so memory system performance can be improved by scheduling memory accesses so that accesses to the same row are performed sequentially.
The present techniques seek to improve the efficiency and/or speed of operation of data processing systems having a cache memory.